Method and device for decoding a sequence of physical signals, reliability detection unit and viterbi decoding unit

ABSTRACT

A method and device for decoding a sequence of physical signals. A Viterbi algorithm is carried out a first time for all physical signals, resulting in a maximum likelihood path, wherein there is one signal value for each physical signal and which has been determined along the entire trellis according to the Viterbi algorithm. A reliability value is determined for each signal value of the maximum likelihood path. The Viterbi algorithm is then carried out a second time with the following steps: selecting one subregion of the trellis, the subregion having a partial initial signal value and a partial end signal value on the maximum likelihood path; determining one further path in that subregion of the trellis which ends at the partial end signal value of the maximum likelihood path; determining each signal value on the further path and comparing same with the corresponding signal value on the maximum likelihood path relating to the same time; depending on the comparison result, the signal value of the maximum likelihood path is allocated the reliability value determined in the previous iteration step or the minimum of this and the reliability value of the partial end signal value; shifting the subregion of the trellis by at least one time unit; and using, storing and/or outputting the determined signal values and selected reliability values associated with the signal values as the decoded sequence.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a method and a device for decoding a sequenceof physical signals.

2. Description of the Related Art

A method such as this and a device such as this are known from G. D.Forney, The Viterbi-Algorithm, Proceedings of the IEEE, Vol. 61, No. 3,pages 268–278, 1973 (hereinafter referred to as “Forney”).

Forney describes the principles of the so-called Viterbi algorithm.

The Viterbi algorithm, which is frequently used for channel decoding ofreceived physical signals that are subject to disturbances, determines asequence of signal values along a so-called trellis for the receivedphysical signals. The probability of the determined sequence of signalvalues corresponding to the sequence of received physical signals is ineach case maximized for the sequence of signal values. The procedurewhich is known from Forney is used to make a decision on a binary basisfor each signal value as to whether a signal value has a first binaryvalue or a second binary value.

The procedure which is known from Forney has the particular disadvantagethat, during the decoding process, it is not evident how reliable thedecision is as to whether the respectively determined signal valueactually corresponds to the originally transmitted signal value.

The method from Forney therefore provides no reliability informationwhatsoever on the quality of the channel decoding process.

In order to improve the method which is known from Forney, it is knownfrom J. Hagenaur, P. Hoeher, A Viterbi Algorithm with Soft-DecisionOutputs and its Applications, pages 1680–1686, GLOBECOM, 1989(hereinafter Hagenaur, et al.) for each determined signal value to beallocated reliability information, which is referred to as a reliabilityvalue in the following text, in the course of the channel decoding ofthe received, noisy (that is to say subject to disturbances) physicalsignal. The reliability value in each case indicates the reliability ofthe respective decision which has been made to classify the receivedsignal as the corresponding signal value. This obviously means that thereliability value indicates the extent to which the received signal issimilar to the first binary signal value or to the second binary signalvalue.

The reliability values are formed, for example, as a function ofso-called state metrics which are calculated while passing through thetrellis in the course of the channel decoding process.

In the method which is known from Hagenauer, et al., the reliabilityvalues are determined in the course of a single run through the Viterbialgorithm.

However, it has been found that this procedure is not optimal,especially and in addition with regard to implementation in hardware.

In order to improve the procedure which is known from Hagenauer, et al.,the method which is described in J. Hagenauer, Source-Controlled ChannelDecoding, IEEE Transaction on Commucications, Vol. 43, No. 9, pages2449–2457, September 1995 (hereinafter “Hagenauer”) has been developed,in which the Viterbi algorithm is run twice, with only the signal valuesbeing determined in the course of the first “run”, and the reliabilityvalues being determined in the course of a second run. The result of thefirst “run” is a “maximum likelihood path” which contains those signalvalues which have been determined using a path traceback method(backtracing method). The signal values which are located on the maximumlikelihood path are used as the decoded physical signals.

In the procedure which is known from Hagenauer, while the second run ofthe Viterbi algorithm is carried out for a large number of further pathsalong the entire trellis, with the further paths all having the samelength as the maximum likelihood path, namely the length correspondingto the sequence of received physical signals, reliability values aredetermined and the respective reliability value associated with thesignal value is determined as a function of the reliability values ofthe signal values of the maximum likelihood path and determinedreliability values for signal values on the further paths.

This procedure is highly complex and, in practice, cannot be used inreal time for the decoding of physical signals, in particular in thefield of mobile radio.

It is also known from C. Berrou, et al., A Low complexity Soft-OutputViterbi Decoder Architecture, ICC 93 (hereinafter “Berrou, et al.”), andU.S. Pat. No. 5,406,570 (hereinafter “U.S. Pat. No. '570”) for theViterbi algorithm not to be carried out for the entire sequence ofphysical signals but only for a partial sequence and for the signalvalues to be determined step-by-step along the trellis, with furtherpaths being formed in the course of the Viterbi algorithm and furtherreliability values being allocated to the determined signal values forthese further paths, which further reliability values are compared withthe reliability values of the signal values on the maximum likelihoodpath, which has not yet been completely determined at this time, on thebasis of which the final reliability values which are associated withthe determined signal values are chosen.

The method which is known from Berrou, et al. and U.S. Pat. No. '570,has the particular disadvantage that convergence of the Viterbialgorithm is not always guaranteed for each of the subregions which aretaken into account in order to determine the further paths.

Another method for determining a maximum likelihood path is known fromPatent Abstracts of Japan JP 11186914 A (hereinafter “JP11186914 A”). Inthis method, a first maximum likelihood path is determined, and anadditional quasi-maximum likelihood path is then chosen, and itsreliability values are compared with those of the first maximumlikelihood path.

Another Viterbi decoder is described in U.S. Pat. No. 5,784,392(hereinafter “U.S. Pat. No. '392).

BRIEF SUMMARY OF THE INVENTION

The invention is thus based on the problem of determining reliabilityvalues for signal values in the course of the Viterbi algorithm, withthe determined reliability values having a reliability which is betterthan that of the known methods in the stochastic sense, or is at leastequivalent to them. Furthermore, it is intended to be possible to usethe method for mobile radio, in which case it is desirable for thecomputation complexity both in software and in hardware to be as low aspossible.

The problem is solved by the method, the device, the reliability valuedetermining unit and the Viterbi decoding unit having the features ofthe independent patent claims.

In a method for decoding a sequence of physical signals, a Viterbialgorithm is carried out a first time for all physical signals. Thefirst “run” of the Viterbi algorithm results in a maximum likelihoodpath which has been determined along the entire trellis that resultsaccording to the Viterbi algorithm. The maximum likelihood path has onesignal value for each physical signal. A reliability value is determinedfor each signal value of the maximum likelihood path determined usingthe Viterbi algorithm. The Viterbi algorithm is now carried out a secondtime, with the following method steps being carried out iterativelyuntil all the signal values of the determined trellis have been takeninto account:

-   -   one subregion of the trellis is selected, with that subregion        having a partial initial signal value and a partial end signal        value on the maximum likelihood path,    -   at least one further path is determined in that subregion of the        trellis which ends at the partial end signal value of the        maximum likelihood path,    -   each signal value on the further path is determined and is        compared with the corresponding signal value on the maximum        likelihood path relating to the same time,    -   depending on the comparison result, the signal value of the        maximum likelihood path is allocated the reliability value        determined in the previous iteration step or the minimum of this        and the reliability value of the partial end signal value,    -   in a subsequent iteration step, the subregion of the trellis is        preferably shifted by at least one time unit.

The determined signal values and the selected reliability valuesassociated with the signal values, as have been determined on the basisof the second run of the Viterbi algorithm, are used and stored and/oroutput as the decoded sequence.

A device for coding a sequence of physical signals has a processor whichis set up such that the method steps, as described above, in the methodfor decoding a sequence of physical signals can be carried out.

A reliability value determining unit for determining a reliability valuein the course of a Viterbi algorithm has a first path memory for storingsignals of a maximum likelihood path according to the Viterbi algorithm.Furthermore, a second path memory is provided, for storing signal valuesof a further path according to the Viterbi algorithm. A first selectionunit is coupled to the first path memory and to the second path memory,and is used for evaluating signal values from the first path memory andfrom the second path memory. A comparison unit is coupled to theselection unit and is used for comparing the chosen signal values fromthe first path memory and those from the second path memory with oneanother. A second selection unit has a control input, a first input anda second input. The control input is coupled to the output of thecomparison unit. The first input is coupled to the output of a thirdselection unit. Furthermore, a reliability value memory is provided forstoring reliability values. A control unit which is also provided is setup such that a previously determined and stored first reliability value,which is associated with a signal value on the maximum likelihood path,can be read from the reliability value memory and can be supplied to afirst input of the third selection unit. Furthermore, the control unitis set up such that a previously determined and stored secondreliability value, which is associated with a signal value on themaximum likelihood path, can be supplied from the reliability valuememory to a second input of the third selection unit. The control unitis furthermore set up such that the first reliability value can besupplied to the second input of the second selection unit. If theselected signal values from the first path memory and from the secondpath memory are not the same, the comparison unit can supply a controlsignal to the second selection unit such that the second selection unitcan select the reliability value which is present at its first input andhas been chosen by the third selection unit.

A Viterbi decoding unit has the reliability value determining unitdescribed above.

The invention results in improved decoding of the sequence of physicalsignals using the Viterbi algorithm. In particular, the quality isimproved, that is to say the stochastic reliability of the reliabilityvalues which are associated with the respective signal values and areoutput as soft decision values by the Viterbi decoder, as a result ofwhich the reliability of the individual signal values for their furtherprocessing is improved.

It should be noted that, according to the invention, the maximumlikelihood path has been determined along the overall trellis thatresults according to the Viterbi algorithm before the Viterbi algorithmis carried out a second time, and that the signal values of furtherpaths are compared with the signal values of the maximum likelihood pathin the course of the second run.

Preferred developments of the invention can be found in the dependentclaims.

The refinements of the invention which are described in the followingtext relate not only to the method, the device and the reliability valuedetermining unit, but also to the Viterbi decoding unit.

A binary value may be used as the signal value. This refinementsimplifies the implementation of the invention since only binary valuesneed be processed, as a result of which, for example, only one bit isrequired for each signal value for the purposes of storing the signalvalues.

A further refinement of the invention provides for at least one initialsignal value to be predetermined at the start of the sequence ofphysical signals and/or for at least one end signal value to bepredetermined at the end of the sequence of physical signals.

A region which has a predetermined number of signal values can beselected as the subregion of the trellis that is to be selected.

According to one refinement of the invention, a number of signal values,with this number being dependent on the reversion depth of theconvolution polynomials that are used, are in each case used as asubregion of the trellis.

The further path can in each case be determined in one iteration byinverting the signal value of the signal value which is passed to therespective partial end signal value according to the maximum likelihoodpath, and a renewed path traceback method is carried out on the basis ofthe partial end signal value, starting with the inverted signal value.The renewed path traceback method makes use of path tracebackinformation which was determined during the first run of the Viterbialgorithm or which occurs once again during the second run.

Each signal value on the maximum likelihood path is compared with thesignal value of the further concurrent path. If the comparison resultsin a match, then the reliability value of the signal value which islocated on the maximum likelihood path is not changed. If the comparisondoes not result in a match, then the minimum of the reliability valuedetermined in a previous iteration and the reliability value of thepartial end signal value is used for the relevant signal value on themaximum likelihood path.

The difference from accumulated signal value metrics which are formedwhile running the Viterbi algorithm may be used as a first approximationof the reliability value.

In one development of the invention, the second selection unit is amultiplexer.

According to a further refinement of the invention, the first selectionunit is set up such that signal values relating to the same time unitare in each case selected.

The third selection unit can be set up such that it selects the lowerreliability value of the first reliability value and the secondreliability value.

According to a further refinement of the invention, the followingcomponents are provided in the device:

-   -   a transition metrics determining unit for determining a        transition metric,    -   an end state metric determining unit, which is coupled to the        transition metric determining unit, for determining an end state        metric,    -   a reliability value determining unit which is coupled to the end        state metric determining unit, and    -   a path traceback unit, which is coupled to the reliability value        determining unit and to the end state metric determining unit,        for determining path traceback information.

Furthermore, a memory can be provided,

-   -   with a memory area for storing path traceback information and/or    -   having a second memory area for storing soft input information        for the decoding unit and/or    -   with a third memory area for storing determined state metrics        and state transition metrics and/or    -   with a fourth memory area for storing signal values which are        intended to be output, and reliability values associated with        the signal values.

At least one of the memory areas may be in the form of RAM, so that therespective memory areas are integrated in the electrical circuit, thusfurthermore considerably speeding up the decoding process.

Furthermore, the path traceback unit may have the following components:

-   -   a control unit, and    -   a multiplexer which is coupled via a control input to the        control unit,        -   in which case it is possible to use the control unit to            select whether information about the maximum likelihood path            or about the respective further concurrent path is selected            by the first multiplexer,        -   in which case the respective start state for the path            traceback method within the further concurrent path can be            supplied to a first input of the first multiplexer,        -   in which case information as to whether a transition bit is            intended to be inverted for the traceback of the further            path can be supplied as a second input of the first            multiplexer,        -   in which case the respective time to which the start state            relates can be supplied at a third input of the first            multiplexer,        -   in which case the respective start state of the maximum            likelihood path can be supplied at a fourth input of the            first multiplexer, and        -   in which case the respective time to which the start state            of the maximum likelihood path relates can be supplied as a            fifth input of the first multiplexer.

One exemplary embodiment of the invention will be explained in moredetail in the following text and is illustrated in the figures, inwhich:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram illustrating the reliability valuedetermining unit according to one exemplary embodiment of the invention.

FIG. 2 shows a block diagram, illustrating the sending, the transmissionand the reception of an electrical physical signal.

FIG. 3 shows a sketch of a butterfly structure, on the basis of whichthe Viterbi algorithm will be explained in more detail.

FIG. 4 shows a block diagram illustrating a path traceback method.

FIG. 5 shows a sketch illustrating the procedure according to theexemplary embodiment of the invention.

FIG. 6 shows a sketch illustrating the procedure according to theexemplary embodiment of the invention, in detail.

FIG. 7 shows a block diagram of a Viterbi decoding unit according to oneexemplary embodiment of the invention.

FIG. 8 shows a sketch of a path traceback unit for the Viterbi decodingunit according to one exemplary embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2 shows, symbolically, a source 201 from which a message 202 isintended to be transmitted from a transmitter 200 to a sink 219 in areceiver 211.

The message 202 to be transmitted is supplied to a source coder 203,where it is compressed such that, although no information is lost,redundant information that is superfluous for the decoding of themessage 202 is eliminated, and the required transmission capacity isthus reduced.

The source coder 202 emits a code word 204uε{±1}^(k),  (1)which consists of a sequence of digital values. In this case, theassumption is made for each code word 204 u that each value u_(i), i=1,. . . , k, of each code word 204 u has an equal probability of assuminga first binary value (logic “0”) or a second binary value (logic “1”).

The code word 204 u is supplied to a unit for channel coding 205, inwhich channel coding of the code word 204 u is carried out. During thechannel coding process, redundant information is deliberately added tothe code word 204 u in order to make it possible to correct, or at leastto identify, any transmission errors which may occur during thetransmission process, thus achieving a high level of transmissionreliability.

The following text is based on the assumption that the channel codingprocess results in each code word 204u∈{±1}^(k)being allocated a channel code word 206c∈{±1}^(n), n>k, n∈N  (2).

The output of the unit for channel coding 205 thus consists of thechannel code word c 206.

The channel code word c 206 is supplied to a unit for modulation 207 ofthe channel code word c 206.

During the modulation process, the channel code word c 206 is associatedwith a functions=

→

  (3)which is suitable for transmission via a physical channel 208.

The modulated signal 209 to be transmitted thus contains both signalinformation and redundant information determined from the signalinformation.

The modulated signal s 209 is transmitted via the physical channel 208to a receiver 211. During the transmission process via the physicalchannel 208, disturbances 210 frequently occur, which corrupt themodulated signal 209 s.

At the receiver 211, this results in a modified modulated signal 212{tilde over (s)}:

→

,  (4)which is supplied to a unit for demodulation 213 in the receiver 211.

The modified modulated signal s 212 is demodulated in the unit fordemodulation 213. The unit for demodulation 213 outputs a vectory∈

^(n),  (5)which is referred to as an electrical signal 214 in the following textand describes the digital, demodulated, modified signal.

The electrical signal y 214 is supplied to a unit for channel decoding215 of the electrical signal y 214, where it is subjected to a Viterbialgorithm (which will be described in the following text) for channeldecoding of the electrical signal y 214. A sequence of electricalsignals y is also referred to in the following text as a sequence ofphysical signals.

The object of the channel decoding process is to carry out so-calledsoft decision decoding. This means that a code word is reconstructedand, furthermore, reliability information (a reliability value) isdetermined for each component, describing the decision made with regardto reconstruction of a component of the code word. A component of thereconstructed code word 216 is referred to in the following text as adigital signal value.

The reconstructed code word 216, that is to say at least one digitalsignal value, is supplied to a unit for source decoding 217, in whichsource decoding is carried out.

Finally, the decoded signal 218 is supplied to the sink 219.

In order to make it easier to understand the invention, the outlinestructure of the Viterbi algorithm will be explained in the followingtext (see FIG. 3). Details of the Viterbi algorithm are described inForney.

For the purposes of this exemplary embodiment, a binary modulated signalis assumed, that is to say the Viterbi algorithm can be run using atrellis which can be implemented by means of a butterfly structure 300,as is illustrated in FIG. 3.

On the basis of the butterfly structure 300, two initial states, a firstinitial state m′ 301 and a second initial state m 302, are in each caseprovided. The first initial state m′ 301 is obtained from the product ofa state index i and the factor 2 (m′=2i) where, if an eight-bit word isto be processed, i=0, . . . , 127 (2⁷), and the second state m 302 isobtained for the respective state index i on the basis m=2i+1.

At a time k, each initial state 301, 302 is allocated a state metric Mso that, for the first initial state m′ 301, the state metric relatingto the time k is thus indicated by M(k, m′=2i) and, for the secondinitial state m 302, the state metric relating to the time k isindicated by M(k, m=2i+1).

Without any restriction to generality, the rest of the description isbased by way of example on the statements relating to the UMTS standard.The statements are equally applicable to the GSM/EDGE standard, with astate in the GSM/EDGE standard being described by 6 bits or 4 bits,respectively.

According to the exemplary embodiment, in which the physical signals aretransmitted in accordance with the UMTS standard, a state with an 8-bitword is preferably described, that is to say, if a_(k) denotes a valueof a bit at the time k, the first initial state is given by 301m′=(a_(k), a_(k−1), a_(k−2), a_(k−3), a_(k−4), a_(k−5), a_(k−6),a′_(k−7)) and the second initial state m 302 is given by m=(a_(k),a_(k−1), a_(k−2), a_(k−3), a_(k−4), a_(k−5), a_(k) _(k−6), a_(k−7)).

Analogously to the procedure in a shift register, a state transitiontakes place by inputting (“shifting from the left”) a new bit valuea_(k+1) relating to the time k+1, symbolized in FIG. 3 by statetransition arrows 303, 304, 305, 306 to a first end state m″ 307 and toa second end state m′″ 308.

The state transition, caused by the “shifting in” of the bit a_(k+1)results, for the first end state 307 relating to the time k+1 (with thestate metric M(k+1, m″=i)) in:m″=(a _(k+1) , a _(k) , a _(k−1) , a _(k−2) , a _(k−3) , a _(k−4) , a_(k−5) , a _(k−6)).The second end state 308 likewise has an associated state metric

${M\left( {{k + 1},{m^{\prime\prime\prime} = {i + \frac{N}{2}}}} \right)}.$

Transition metrics I1, I2, I3, I4 are determined using the Viterbialgorithm.

As can be seen, I1 clearly indicates the probability for a statetransition to the state m″ when the bit a_(k+1) has the logic value“zero” and the trellis was in the first initial state m′ 301.

As can be seen, I2 clearly indicates the probability of a statetransition to the state m″ when the bit a_(k+1) has the logic value“zero” and the trellis was in the second initial state m 302.

As can be seen, I3 denotes the probability of a state transition to thestate m′″ when the bit a_(k+1) has the logic value “one” and the trelliswas in the first initial state m′ 301.

As can be seen, I4 denotes the probability of a state transition to thestate m′″ when the bit a_(k+1) has the logic value “one” and the trelliswas in the second initial state m 302.

The new state metrics for the two end states m″ and m′″ are obtainedusing the Viterbi algorithm in accordance with the following rules:M(k+1, m″=i)=max(M(k, m′=2i)+I1, M(k, m=2i+1)+I2),

${{M\left( {{k + 1},{m^{\prime\prime\prime} = {i + \frac{N}{2}}}} \right)} = {\max\left( {{{M\left( {k,{m^{\prime} = {2i}}} \right)} + {I\; 3}},{{M\left( {k,{m = {{2i} + 1}}} \right)} + {I4}}} \right)}},$where N denotes the number of states in the trellis, that is to say, for8 bits, N=256 states.

In accordance with the Viterbi algorithm, a forward determinationprocess is used, starting at a defined initial state which according tothe UMTS standard comprises a number, which can be predetermined, ofbits with the logic value “0”, for a successive determination processsuch that the state metrics for one point in time are determined for allthe initial states of the trellis, and the respective state transitionmetrics are determined in accordance with the butterfly structure 300.

Once the two state transition metrics have each been determined whichboth lead to the same end state starting from different initial states,then the sum of the respective state metrics and transition metrics isin each case formed, and the larger sum is selected and is allocated asthe state metric to the corresponding end state 307, 308.

The bit a′_(k−7), a_(k−7) of the respective initial state selected bythe maximum selection process is stored in a path traceback register.

The method described above is carried out for all the states and all thetime steps in the trellis until the overall end state of the sequence ofphysical signals, as defined in accordance with the UMTS standard, isreached. The overall end state of the sequence of physical signals inaccordance with the UMTS standard is once again a predetermined numberof bits with the logic value “zero” (the sequence of physical signals isterminated and is also referred to as “tail bits”).

Thus, as can be seen, based on the forward method, the informationrelating to the selected path of the two state transitions, or expressedin other words information about the initial state which has passedthrough the state transition to the respective end state of thebutterfly structure 300, is thus in each case stored. The respective endstate and the corresponding initial state differ only in two bits, inthe following manner:

One new bit has been shifted into the “shift register” (the bit a_(k+1))and one bit (the “oldest”, that is to say the least significant bita′_(k−7) or a_(k−7), which is referred to as the transition bit in thefollowing text) has been shifted out of the “shift register”.

Since the bit a_(k+1) that has been shifted in is part of the directdesignation of the respective end state, it is sufficient to store onlythe transition bit a′k⁻⁷ or a_(k−7) in the path traceback register inorder to make it possible to uniquely determine the maximum likelihoodpath as described in the following text.

During the path traceback method, the transition bits a′_(k−7) anda_(k−7) are used in conjunction with the knowledge about the overall endstate of the Viterbi algorithm which, in accordance with the UMTSstandard, ends in the overall end state with the logic value “zero”, inorder to reconstruct the maximum likelihood path in the trellis.

As is shown in FIG. 4, a start state 401 is known for the path tracebackmethod, with the assumption being made that the path traceback method isstarted at the time k. The start state 401 is denoted by the bits a_(k),a_(k−1), a_(k−2), a_(k−3), a_(k−4), a_(k−5), a_(k−6), a_(k−7) and formsa pointer 402 to an address in a path traceback register 404 for thetime step k, which contains 256 values for a word length of 8 bits. 256bits are stored for the time step k in the path traceback register 404and can each be addressed uniquely by the 8 bits of the start state 401.

The addressed bit 403 in the path traceback register 404 for the time kis read, and the 8 bits a_(k), a_(k−1), a_(k−2), a_(k−3), a_(k−4),a_(k−5), a_(k−6), a_(k−7), which form the start state 401 relating tothe time k, are shifted “from the right” into the shift register. Themost significant bit a_(k) relating to the time k is accordingly shiftedout of the shift register and is used as the decoded signal value 405relating to the time k.

The new word which is located in the shift register and which forms apath traceback state 406 relating to the time k−1 (a_(k−1), a_(k−2),a_(k−3), a_(k−4), a_(k−5), a_(k−6), a_(k−7), selected bit 403 from thepath traceback register 404 relating to the time k) is once again usedas a pointer 407 to a bit in a path traceback register 408 for the timek−1. The addressed bit 409 in the path traceback register 408 for thetime k−1 is read, and a further state transition takes place in afurther path traceback state relating to the time k−2. The mostsignificant bit a_(k−1) relating to the time k−1 is accordingly shiftedout of the shift register and is used as the decoded signal value 410relating to the time k−1.

The method sketched above is carried out for all the points in timeuntil the initial state of the trellis, that is to say the time at whichthe first physical signal was received, has been determined.

It should be noted that each path traceback register relating to eachtime with a word length of 8 bits has 256 bits for 256 states in eachcase.

Based on this first “run” of the Viterbi algorithm, the path tracebackmethod results in the so-called maximum likelihood path 501.

Once the maximum likelihood path 501 shown in the trellis 500 in FIG. 5has been determined, the Viterbi algorithm is carried out a second time,based on the procedure described in the following text.

FIG. 5 shows the respective states with the reference symbol 502 for onetime step in each case for the trellis 500.

The maximum likelihood path 501 contains the signal values determinedusing the path traceback method and which are used as the decodedphysical signals, that is to say as the decoded sequence of the physicalsignals.

As is illustrated in FIG. 5, the subregion 503 is selected from theoverall trellis 500.

The aim of the method described in the following text is to determinethe reliability values associated with the individual signal values, inthe sense of a “worst case estimate”.

In the following text, the signal values of the maximum likelihood path501 are denoted Pr.TB(k−i) where k−i denotes the times k, k−1, k−2, . .. , k−i that are located in the selected subregion 503. i denotes asequential index for the times in the subregion 503.

As can be seen, the subregion 503 may be regarded as a window which isin each case shifted by one time step, commencing at the start of thetrellis 500 and being shifted through to the end of the trellis 500.

According to the exemplary embodiment, a second path is formed relatingto the partial end state 504 of the maximum likelihood path 501 whichcorresponds to the signal value relating to the time k.

As has been described above, the bit value which has been shifted intothe shift register from a previous initial state 505 in order to reachthe partial end state 504 on the maximum likelihood path 501 is in factknown.

In order to determine a second path 506 within the trellis 500 for theselected subregion 503 relating to the time k, the transition bit whichdescribes the transition from the state 505 to the partial end state 504on the maximum likelihood path 501 is inverted, and a renewed pathtraceback method is carried out with the inverted bit, using the storedpath traceback register for the time k (see FIG. 4). This is done in thesame way, as described above in conjunction with FIG. 4, as far as theinitial state of the trellis.

The result is the second path 506, which contains states 507.

Once the second path has been determined as far as the partial end state504, a first reliability value is determined for the partial end state504 in the selected subregion 503 for the time step k.

The first reliability value is obtained from the difference between thestate metric of the partial end state 504 for the situation where themetric has been determined via the states of the maximum likelihood path501, and the state metric for the partial end state 504 for thesituation where the state metric has been determined via the states 507along the second path 506.

As can be seen, this difference represents a measure of the decisioncertainty for the transition along the maximum likelihood path 501.

If, by way of example, the difference is very small, then this means itwould also have been possible to reach that state directly via thesecond path 506 without involving a statically large error.

However, if the difference is very high, then this is an indication thatthe decision for the corresponding bit, that is to say the state of themaximum likelihood path 501, is highly reliable.

First reliability values, which still need to be corrected, are thusdetermined with respect to the time k for all states on the maximumlikelihood path 501.

The following method is in each case carried out along the directionsymbolized by the arrow 508 in FIG. 5, for a time k−n, n=1, . . . , sizeof the selected subregion, for the state on the maximum likelihood path501, and with regard to the state on the second path 506:

-   -   A check is carried out to determine whether the signal value,        that is to say the bit, which has been decoded on the basis of        the maximum likelihood path 501 is the same as the bit which        would have been decoded on the basis of the second path 506.    -   If this is the case, then the first reliability value remains        unchanged for the signal value of the respective state on the        maximum likelihood path 501.    -   If the decoded bits relating to a time k−n on the maximum        likelihood path 501 and on the second path 506 have different        values, then the minimum of the first reliability value which is        associated with the respective state on the maximum likelihood        path 501 relating to the time k and that of the corresponding        state on the maximum likelihood path 501 relating to the        respective time k—n is determined and is allocated as a new        first reliability value to the signal value on the maximum        likelihood path 501 relating to the time k−n.    -   This method is carried out along the maximum likelihood path 501        and along the second path 506 for all the states on the maximum        likelihood path 501 within the selected subregion 503.

This procedure is carried out for the subregion 503 in each iteration,with the subregion 503 in each case being shifted by one time step alongthe trellis 500 in the direction of the overall end state of thesequence of physical signals.

The iterative procedure will be explained further, in detail, inconjunction with FIG. 6.

FIG. 6 shows the trellis 500 as well as the maximum likelihood path 501.

In FIG. 6, it is assumed that the method starts at a first time stepk=0.

In a first step, a first subregion 601 is selected, which contains thestates for two times (k=0, k=1).

As shown in FIG. 6, the first subregion 601 thus contains a first branch602 of the maximum likelihood path 501.

A second path 604, which has only one branch 605, is determined usingthe method described above by inversion of the transition bit, startingwith the partial end state 603 of the first subregion 601.

The reliability value S(1) is now determined for the first partial endstate 603 by forming the difference of the metrics Ms(k=1,m1) for themaximum likelihood path 602 and Mc(k=1,m1) for the second path 604,where Ms(1,m1) accordingly denotes the total metric for the accumulatedstate metrics and transmission metrics along the maximum likelihood path501 as far as the first partial end state 603, generally as far as thestate m relating to the time k Ms (k, m). Mc(k,m) in a correspondingmanner denotes the total metric of the accumulated state metrics andtransition metrics along the second path 604 as far as the secondpartial end state 603, in general as far as the state m relating to thetime k.

The first iteration is ended after forming the first reliability valuefor the time k=1 (S(1)).

A second subregion 606 is selected in a second iteration, which nowcontains the states of the trellis 500 for the times k=0, k=1, k=2.

In the second iteration, the selected second subregion 606 has a secondpartial end state 607 on the maximum likelihood path 501.

On the basis of the second partial end state 607, a new path, which isreferred to in the following text as the third path 608, is now onceagain determined by means of the conventional path traceback methodusing the path traceback register. Furthermore, both the statetransition metrics for the second branch 618 of the maximum likelihoodpath 501, which assesses the state transition from the second partialend state 603 to the second partial end state 607, are determined.

Furthermore, the state metric for the state 610 and the state transitionmetric for the second partial end state 607, which is located on thethird path 608, are determined along the third path 608.

The first reliability value S(2) for the time k=2 for the second partialend state 607 is once again determined using the following rule:S(2)=Ms(2,m2)−Mc(2,m2).

In a further step, a check is carried out to determine whether thedecoded bit for the time k=1 along the third path 608 starting from thesecond partial end state 607 is the same as the decoded bit for themaximum likelihood path 501 relating to the time k=1.

If they are not the same, the minimum is formed between the reliabilityvalue S(1), which is associated with the first partial end state 603,and the first reliability value S(2) which is associated with the secondpartial end state 607.

In a further step, the minimum value is allocated to the first partialend state 603.

This completes the second iteration.

In a third iteration, the window (the subregion) is shifted to the rightby one further time step, as can be seen, that is to say the selectedthird subregion 611 now contains states from four times, namely k=0,k=1, k=2, k=3.

The method described above is carried out starting from a third partialend state 612, such that a fourth path 613 is determined by means of afurther path traceback method using the corresponding path tracebackregister.

The total metric along the fourth path 613, which is also referred to asthe concurrent path in the following text, is known from the statemetric of the state 616 and from the state transition metric in thethird partial end state 612.

Furthermore, the state transition metric is determined for the statetransition from the second partial end state 607 to the third partialend state 612, symbolized by the third branch 617 on the maximumlikelihood path 501. The total metric along the maximum likelihood path501 is accordingly also known from the state metric for the secondpartial end state 607.

The first reliability value for the third partial end state 612 isformed using the following rule:S(3)=Ms(3,m3)−Mc(3,m3).

Once the first reliability value S(3) for the third partial end state612 has been determined, the respective first reliability value is or isnot updated in accordance with the procedure described above for all thestates which are located in the third subregion 611 on the maximumlikelihood path 501.

This completes the third iteration.

In the fourth iteration, the subregion is once again shifted by one timestep in the direction of the end of the trellis 500, so that a fourthsubregion 619 is chosen, which now contains states from five times k=0,k=1, k=2, k=3, k=4.

A fifth path 621 relating to a fourth partial end state 620 on themaximum likelihood path 501 is determined using the above procedure.

The first reliability value S(4) for the fourth partial end state 620 isthen determined using the following rule:S(4)=Ms(4,m4)−Mc(4,m4).

Starting from the fourth partial end state 620, the first reliabilityvalue is in each case updated or is not updated, in accordance with theprocedure described above, successively for previous states in time.

Expressed in the form of an if/then request in a programming language, afirst reliability value for a respective partial end state relating to atime k is or is not updated on the basis of the following condition:If (Sec.TB(n_upd_(—) k)=Pr.Tb(n))ThenS(n)=S(n)ElseS(n)=min (S(n), S(k))End If-Then loop.

Sec.TB(n_upd_k) denotes the decoded bit relating to the time n on therespective concurrent path (second path, third path, fourth path, . . .) during the updating iteration k starting from a partial end state onthe maximum likelihood path 501 relating to the time k.

As can be seen, the procedure can be explained by the followingheuristic knowledge:

The respective first reliability value at the start of the iteration isthe upper limit of the reliability value that is to be output. Thesmaller is the estimated reliability value for the respective partialend state, the more probable it is that that the partial end state canalso be reached via the respective further path. The intermediatereliability value for a state on the maximum likelihood path 501 musttherefore be updated within the selected subregion if the correspondingdecoded bit relating to the corresponding time differs between themaximum likelihood path 501 and the further path.

Once the reliability values for all the states along the maximumlikelihood path 501 have been updated, the time window, that is to saythe subregion, is shifted by one time step further in the direction ofthe end of the trellis.

The new reliability value for the corresponding partial end staterelating to the time k+1 is estimated, the corresponding new furtherpath is determined, and the corresponding state metrics and statetransition metrics are determined and, once again, the reliabilityvalues for the states on the maximum likelihood path 501 within thesubregion of the k+1th iteration are updated.

It should be noted that the most recently updated value of the previoussubregion in time is finally determined, and is no longer considered infurther iterations.

The reliability values of all the states in the time window on themaximum likelihood path 501 are updated in each iteration depending onthe rule described above until the corresponding state falls out of thetime window when shifted further.

FIG. 7 shows a block diagram of the Viterbi soft decision decoding unit700 according to the exemplary embodiment of the invention.

The Viterbi decoding unit 700 is clocked via a clock input 701 by anexternal controller (not shown), for example a signal processor at afrequency of 52 MHz.

The Viterbi decoding unit 700 has an internal control unit 702, a unit703 for storing the information relating to the decoding method(convolution polynomials), a transition metric determining unit 704, anend state metric determining unit 705, a reliability value determiningunit 706, and a path traceback unit 707.

Furthermore, a memory 708 is provided, which is subdivided into varioussubregions, for storing the soft input values, the traceback informationas well as the decoding bits and their reliability information.

In addition, a memory is provided for storage of the temporaryinformation, such as start metrics.

The transition metric determining unit 707 uses the decodinginformation, which is stored in the unit 703 for storing the informationrelating to the decoding method, for each transition in the trellis toform the theoretical coded output information, and combines this withthe received soft input values from the memory to form the transitionmetric values using the following rule:(2x ₁−1)S1+(2x ₂−1)+(2x ₃−1)S3where

-   -   S1, S2, S3 denote the soft input values for the decoder, and    -   x₁, x₂, X₃ denote the theoretically coded output information.

The end state metric determining unit 705 is coupled to the transitionmetric determining unit 704 such that the determined state transitionmetrics can be supplied to it. The end state metric determining unit 705contains four adders 709, 710, 711, 712, two units 713, 714 for forminga maximum value from two previously formed sums, as well as a pathtraceback register 715, which are formed on the basis of the butterflystructure 300 illustrated in FIG. 3.

The respective bits which result from the choice of the maximum sum fromthe state metric for the respective initial state of the butterflystructure 300 and from the state transition metric and are thus shiftedout of the shift register on the basis of the method described above arestored in the path traceback register 715.

The reliability values are determined by the reliability valuedetermining unit 706, which is coupled to the control unit 702 and isillustrated in detail in FIG. 1, using the method described above, andare stored in a second memory area 717 for storing the reliabilityvalues and the intermediate reliability values, which may still bechanged during the iterations.

Furthermore, the reliability value determining unit 706 is coupled tothe path traceback unit 707 such that the corresponding bit, that is tosay the transition bit for the respective time step for the states alongthe respective further path relating to the time stamp k, is suppliedfrom the path traceback unit 707 to the reliability value determiningunit 706, as will be explained in the following text, in each case via afirst input 718, and the transition bit for the respective states on themaximum likelihood path is supplied from the path traceback unit 707 tothe reliability value determining unit 706 via a second coupling 719.

The respectively determined state metrics and state transition metricsare stored in a third memory area 720.

Signal values that are intended to be output and final reliabilityvalues which are associated with the signal values are stored in afourth memory area 721.

The individual components are coupled to one another via a bus 722.

FIG. 1 shows a sketch of the reliability value determining unit 706, indetail. When the subregion has the maximum size of 45 time units, thereliability value determining unit 706 according to the exemplaryembodiment has a first register 101 for storing the bits, decoded on thebasis of the selected subregion, for the state transitions along themaximum likelihood path.

The decoded bits are stored in a second register 102, likewise with alength of 45 bits, according to the path traceback method, along therespectively determined concurrent path within the selected subregion.

One bit from the first register 101 and one bit from the second register102, which each describe a decoded bit relating to the same time, are ineach case read via a selection unit (not shown) firstly along themaximum likelihood path 501 and along the further concurrent path. Thesebits are supplied via two couplings, a first coupling 103 and a secondcoupling 104, to an exclusive-OR gate as the comparison unit 105.

One output 106 of the comparison unit 105 is connected to a controlinput 107 of a multiplexer 108. A first input 109 of the multiplexer 108is coupled to an output 110 of a minimum selection unit 111. A firstinput 112 of the minimum selection unit 111 is coupled to a reliabilityvalue memory 113. A second input 114 of the minimum selection unit 111is likewise coupled to the reliability value memory 113. Furthermore, asecond input 115 of the multiplexer 108 is likewise coupled to the firstinput 112 of the minimum selection unit 111, so that the reliabilityvalue which is present at the first input 112 of the minimum selectionunit 111 is also present at the second input 115 of the multiplexer 108.

One output 116 of the multiplexer 108 is likewise coupled to thereliability value memory 113.

The control unit 702 controls the reliability value determining unit 706such that the first reliability value is formed by a subtraction unit117 in each case for a time k and a state m on the maximum likelihoodpath, and is stored as the first reliability value S(k) for therespective iteration in which the time step k describes the time step inwhich the respective partial end state is located.

Furthermore, the reliability value memory 113 is used to store thereliability values and intermediate reliability values S(k−i) determinedusing the method described above.

The corresponding total metrics for the respective partial end statealong the maximum likelihood path 501 are supplied by the end statemetric determining unit 705 to the reliability value determining unit706.

Once the first reliability value S(k) relating to the time k has beendetermined, the control unit 702 selects reliability values S(k−i) whichhave not been updated relating to the time k−i, and supplies these tothe first input 112 of the minimum selection unit 111.

The first reliability value S(k) is supplied to the second input 114 ofthe minimum selection unit 111.

The minimum of the two reliability values is thus produced at the output110 of the minimum selection unit 111, and is hence also applied to thefirst input 109 of the multiplexer 108.

The reliability value S(k−i) is applied to the second input 115 of themultiplexer 108.

If the check which is carried out by means of the exclusive-OR gate 105results in the two selected bits from the first register 101 and fromthe second register 102 differing, then the multiplexer 108 is switchedby the output signal from the exclusive-OR gate 105 such that the signalwhich is applied to the first input 109 of the multiplexer 108 is passedthrough to the output 116 of the multiplexer 108, and this valuereplaces the previous reliability value S(k−i), which was applied to thefirst input 112 of the minimum selection unit 111, as the updatedreliability value S(k−i)_upd.

The reliability value memory 113 is coupled via the bus 722 to thefourth memory area 721 so that, after carrying out the second “run” ofthe Viterbi algorithm, the determined reliability values are stored inthe fourth memory area 721.

FIG. 8 shows the path traceback unit 707 in detail.

The path traceback unit allows both the maximum likelihood path and thefurther concurrent paths to be traced back. This correspondingly meansthat input signals exist which refer to both path types and which can besupplied in multiplexed form to the internal logic state.

The path traceback unit 707 has a first multiplexer 801 which is coupledvia a control input 802 to the control unit 702 (see FIG. 7). Thecontrol input 802 is used to select whether information relating to themaximum likelihood path 501 or relating to the respective furtherconcurrent path is selected by the first multiplexer 801. A stop signalfor stopping the processing of information relating to the further pathis supplied to the multiplexer 801 via a first stop input 803. A stopsignal for stopping the processing of information relating to themaximum likelihood path 501 is supplied to the multiplexer 801 via asecond stop input 804.

The respective start state for the path traceback method within thefurther path is supplied to the multiplexer 801 at a first input 805.

The information as to whether the first transition bit need be invertedfor tracing back the further path is supplied to the first multiplexer801 via a second input 806. The second input 806 is active at the startof the traceback method via the concurrent path, and is inactive duringthe rest of the traceback method.

The respective time k to which the start state relates is supplied tothe first multiplexer 801 via a third input 807.

The start state for the maximum likelihood path 501 is supplied to thefirst multiplexer 801 via a fourth input 808.

The time to which the start state of the maximum likelihood path 501relates is supplied to the first multiplexer 801 via a fifth input 809.

A stop signal 810 is supplied from the first multiplexer 801 to thecontrol unit 703 and is used to indicate the completion of the pathtraceback method.

The address of the respective path traceback register 715 to be readwithin the first memory area 716 is produced by the control unit 703,and the corresponding bits of the selected path traceback register 715are read in as input data 811 from the RAM and are supplied to a secondmultiplexer 812.

The second multiplexer 812 is controlled by the control unit 703 via acontrol input 813. The start conditions, which are selected by the firstmultiplexer 801, that is to say the respective start state and therespective start time, are supplied to a first input 814 of a thirdmultiplexer 815.

The third multiplexer 815 thus receives start information from themaximum likelihood path or from the concurrent path.

The third multiplexer 815 is controlled by the control unit 703 via acontrolled input 816 of the third multiplexer 816.

The start conditions of the input 814 of the third multiplexer 815select one bit from the path traceback register for the start time asshown in FIG. 4 (403), which is referred to as the “traceback value” oras the “transition bit”, which is attached to the current state vectoron the right and thus forms the new pointer value 818. From now on, therespective pointers which are supplemented in each time step select thetransition bit of the respectively previous time step.

A second input 817 of the third multiplexer 815 is supplied with a valuewhich represents the respectively new pointer value 818 of the previoustime step in time and of the state in the trellis 500 on the basis ofthe path traceback register 715 loaded into the second multiplexer 812,and on the basis of the associated transition bit which is determined bythe pointer for determining the transition bit 819.

The path traceback unit requires information relating to the codingmethod that is used, such as the number of states and hence the numberof bits in the state vector. This information is required not only forproducing the new pointer value but also for preselection of the pathtraceback register 715 (size of the path traceback register 715).

The bit which is shifted out on the basis of the path traceback methoddescribed above is used as a decoded bit, which corresponds to thecorresponding signal value on the maximum likelihood path or on thefurther path.

The decoded bit 820, that is to say the bit which is shifted out of thecorresponding shift register, is supplied to an input 822 of a fourthmultiplexer 821.

The bit is supplied to a first output 824 or to a second output 825depending on a control signal at a control input 823 of the fourthmultiplexer 821. If the bit is supplied to the first output 824, thenthis means that the bit is associated with the further path. If the bitis supplied to the second output 825, then this means that the bit isassociated with the associated likelihood path.

The control unit 702 is set up such that the method steps describedabove can be carried out by the reliability value determining unit 706and the corresponding further units of the Viterbi decoding unit 700.

The following publications are cited in this document:

-   Forney G. D. Forney, The Viterbi-Algorithm, Proceedings of the IEEE,    Vol. 61, No. 3, pages 268–278, 1973-   [2] J. Hagenauer, P. Hoeher, A Viterbi Algorithm with Soft-Decision    Outputs and its Applications, pages 1680–1686, GLOBECOM, 1989-   [3] J. Hagenauer, Source-Controlled Channel Decoding, IEEE    Transaction on Communications, Vol. 43, No. 9, pages 2449–2457,    September 1995-   [4] C. Berrou et al, A Low Complexity Soft-Output Viterbi Decoder    Architecture, ICC 93.-   [5] U.S. Pat. No. 5,406,570-   [6] Patent Abstracts of Japan JP 11186914 A-   [7] U.S. Pat. No. 5,784,392

LIST OF REFERENCE SYMBOLS

-   101 First register-   102 Second register-   103 First coupling-   104 Second coupling-   105 Comparison unit-   106 Comparison unit output-   107 Multiplexer control input-   108 Multiplexer-   109 Multiplexer first input-   110 Minimum selection unit output-   111 Minimum selection unit-   112 Minimum selection unit first input-   113 Reliability value memory-   114 Minimum selection unit second input-   115 Multiplexer second input-   116 Multiplexer output-   200 Transmitter-   201 Source-   202 Message-   203 Source coder-   204 Code word-   205 Unit for channel coding-   206 Channel code word-   207 Unit for modulation 207 of the channel code word-   208 Physical channel-   209 Modulated signal-   210 Disturbance-   211 Receiver-   212 Modified modulated signal-   213 Unit for demodulation-   214 Electrical signal-   215 Unit for channel decoding-   216 Reconstructed code word-   217 Source decoding-   218 Decoded signal-   219 Sink-   300 Butterfly structure-   301 First initial state-   302 Second initial state-   303 State transition arrow-   304 State transition arrow-   305 State transition arrow-   306 State transition arrow-   307 First end state-   308 Second end state-   I1 First state transition metric-   I2 Second state transition metric-   I3 Third state transition metric-   I4 Fourth state transition metric-   401 Start state path traceback method-   402 Pointer to a bit in the path traceback register for the time k-   403 Bit in the path traceback register for the time k-   404 Path traceback register for the time k-   405 Decoded signal value for the time k-   406 Path traceback state for the time k−1-   407 Pointer to a bit in the path traceback register for the time k−1-   408 Path traceback register for the time k−1-   409 Bit in the path traceback register for the time k−1-   410 Decoded signal value for the time k−1-   500 Trellis-   501 Maximum likelihood path-   502 States in the trellis-   503 Subregion-   504 Partial end state-   505 State preceding the partial end state on the maximum likelihood    path-   506 Second path-   507 States of the second path-   508 Arrow-   Pr.TB(k−j) Transition bit on the maximum likelihood path-   Sec.TB(k−j) Transition bit on the second path-   601 First subregion-   602 First branch maximum likelihood path-   603 First partial end state-   604 Second path-   605 Branch on second path-   606 Second subregion-   607 Second partial end state-   608 Third path-   609 State on the third path-   610 State on the third path-   611 Third subregion-   612 Third partial end state-   613 Fourth part-   614 State of the fourth path-   615 State of the fourth path-   616 State of the fourth path-   617 First branch on the maximum likelihood path-   618 Second branch on the maximum likelihood path-   619 Fourth subregion-   620 Fourth partial end state-   621 Fifth path-   622 State on the fifth path-   623 State on the fifth path-   624 State on the fifth path-   625 State on the fifth path-   700 Viterbi decoding unit-   701 Clock input-   702 Control unit-   703 Signal reception memory-   704 Metric determining unit-   705 End state determining unit-   706 Reliability value determining unit-   707 Path traceback unit-   708 Memory-   709 Adder-   710 Adder-   711 Adder-   712 Adder-   713 Maximum selection unit-   714 Maximum selection unit-   715 Path traceback register-   716 First memory area-   717 Second memory area-   718 First coupling-   719 Second coupling-   720 Third memory area-   721 Fourth memory area-   722 Bus-   801 First multiplexer-   802 Multiplexer control unit-   803 First stop input-   804 Second stop input-   805 First multiplexer first input-   806 First multiplexer second input-   807 First multiplexer third input-   808 First multiplexer fourth input-   809 First multiplexer fifth input-   810 Stop signal-   811 Input data-   812 Second multiplexer-   813 Second multiplexer control input-   814 Third multiplexer first input-   815 Third multiplexer-   816 Third multiplexer control input-   817 Third multiplexer second input-   818 New pointer value for the next state in time in trellis-   819 Transition bit-   820 Decoded bit-   821 Fourth multiplexer-   822 Fourth multiplexer input-   823 Fourth multiplexer control input-   824 Fourth multiplexer first output-   825 Fourth multiplexer second output-   901 Trellis half-   802 First subregion-   903 Second subregion

1. A method for decoding a sequence of physical signals, comprising:carrying out a Viterbi algorithm a first time for all physical signals,as a result of which a maximum likelihood path is determined along theoverall trellis which results on the basis of the Viterbi algorithm, andwith one signal value being determined for each physical signal;determining a reliability value for each signal value of the maximumlikelihood path determined on the basis of the Viterbi algorithm;carrying out the Viterbi algorithm a second time, with the followingmethod steps being carried out iteratively until all the signal valuesof the determined trellis have been taken into account: a) selecting onesubregion of the trellis, with that subregion having a partial initialsignal value and a partial end signal value on the maximum likelihoodpath; b) determining at least one further path in that subregion of thetrellis which ends at the partial end signal value of the maximumlikelihood path; c) comparing each signal value on the further path witheach signal value on the maximum likelihood path; d) forming the minimumof the reliability value associated with the signal value and of thereliability value of the partial end signal value for each signal valueon the maximum likelihood path, wherein e) the reliability value or theminimum is selected and is associated with the respective signal valueaccording to a predetermined criterion; and using the determined signalvalues and the selected reliability values associated with the signalvalues as the decoded sequence.
 2. The method as claimed in claim 1, inwhich a binary value is used as the signal value.
 3. The method asclaimed in claim 1, in which at least one initial signal value ispredetermined at the start of the sequence of physical signals and/or atleast one end signal value is predetermined at the end of the sequenceof physical signals.
 4. The method as claimed in claim 1, in which anarea which has a predetermined number of signal values is in each caseselected as the subregion of the trellis.
 5. The method as claimed inclaim 4, in which a number of signal values are each used as onesubregion of the trellis, with this number being dependent on thereversion depth of the convolution polynomial that is used.
 6. Themethod as claimed in one of claims 1 to 5, in which the further path isdetermined in the following way: inverting the transition bit which hasled to the partial end signal value according to the maximum likelihoodpath; carrying out a path traceback method is by means of path tracebackinformation which was determined during the first run of the Viterbialgorithm and during the current run of the Viterbi algorithm, based onthe partial end signal value, and with the renewed path traceback methodbeing started with the inverted transition bit.
 7. The method as claimedin claim 6, in which the difference between accumulated signal valuemetrics which are formed on the basis of the Viterbi algorithm is usedas the reliability value.
 8. The method as claimed in claim 7, in whichthe difference between accumulated signal value metrics or the minimumof the reliability value and the reliability value of the partial endsignal value is in each case chosen for the signal value, and isassociated with the signal value.
 9. A reliability value determiningunit for determining a reliability value in the course of a Viterbialgorithm, comprising: a first path memory for storing signal values ofa maximum likelihood path on the basis of the Viterbi algorithm; asecond path memory for storing signal values of a further path on thebasis of the Viterbi algorithm; a first selection unit, which is coupledto the first path memory and to the second path memory, for selectingsignal values from the first path memory and from the second pathmemory; a comparison unit, which is coupled to the first selection unit,for comparing the selected signal values from the first path memory andfrom the second path memory; a second selection unit which has, a) acontrol input which is coupled to the output of the comparison unit, b)a first input which is coupled to the output of a third selection unit,c) a second input; a reliability value memory for storing reliabilityvalues; and a control unit which is set up such that a) a previouslydetermined and stored first reliability value, which is associated witha signal value on the maximum likelihood path, can be supplied from thereliability value memory to a first input of the third selection unit,b) a previously determined and stored second reliability value which isassociated with a signal value on the maximum likelihood path can besupplied from the reliability value memory to a second input of thethird selection unit, c) the first reliability value can be supplied tothe second input of the second selection unit, d) the value which isselected by the second selection unit can be stored as the firstreliability value; in which case, if the selected signal values from thefirst path memory and from the second path memory are not the same, thecomparison unit can supply a control signal to the second selection unitsuch that the second selection unit can select that reliability valuewhich is applied to its first input and has been selected by the thirdselection unit.
 10. The reliability value determining unit as claimed inclaim 9, in which the control unit is set up such that a previouslydetermined and stored second reliability value, which is associated withthe partial end signal value of the maximum likelihood path, can besupplied from the reliability value memory to the second input of thethird selection unit.
 11. The reliability value determining unit asclaimed in claim 9, in which the second selection unit is a multiplexer.12. The reliability value determining unit as claimed in claim 9, inwhich the first selection unit is set up such that signal values are ineach case selected for the same time unit.
 13. The reliability valuedetermining unit as claimed in claim 9, in which the third selectionunit is set up such that it selects the lower reliability value of thefirst reliability value and the second reliability value.
 14. Thereliability value determining unit as claimed in claim 9, in which thecontrol unit is set up such that the reliability values of all thesignal values of the maximum likelihood path can be supplied iterativelyas the first reliability value to the first input of the third selectionunit.
 15. A Viterbi decoding unit having a reliability value determiningunit as claimed in one of claims 9 to
 14. 16. A device for decoding asequence of physical signals, having a processor which is set up suchthat the following method steps can be carried out: determining amaximum likelihood path along the overall trellis which results on thebasis of the Viterbi algorithm for all the physical signals based on afirst run of a Viterbi algorithm, as a result of which one signal valueis determined for each physical signal; determining a reliability valuefor each signal value of the maximum likelihood path determined on thebasis of the Viterbi algorithm; carrying out the Viterbi algorithm asecond time, with the following method steps being carried outiteratively until all the signal values of the determined trellis havebeen taken into account: a) selecting one subregion of the trellis, withthat subregion having a partial initial signal value and a partial endsignal value on the maximum likelihood path; b) determining at least onefurther path in that subregion of the trellis which ends at the partialend signal value of the maximum likelihood path; c) comparing eachsignal value on the further path with each signal value on the maximumlikelihood path; d) forming the minimum of the reliability valueassociated with the signal value and of the reliability value of thepartial end signal value for each signal value on the maximum likelihoodpath, wherein e) the reliability value or the minimum is selected and isassociated with the respective signal value according to a predeterminedcriterion; and using the determined signal values and the selectedreliability values associated with the signal values as the decodedsequence.
 17. The device as claimed in claim 16, further comprising: atransition metrics determining unit for determining a transition metric;an end state metric determining unit, which is coupled to the transitionmetric determining unit, for determining an end state metric; areliability value determining unit which is coupled to the end statemetric determining unit; and a path traceback unit, which is coupled tothe reliability value determining unit and to the end state detectionmetric determining unit, for determining path traceback information. 18.The device as claimed in claim 16 or 17, having further comprising amemory with a memory area for storing path traceback information; havinga second memory area for storing soft input information for the decodingunit; and/or with a third memory area for storing determined statemetrics and state transition metrics; with a fourth memory area forstoring signal values which are intended to be output, and reliabilityvalues associated with the signal values.
 19. The device as claimed inclaim 18, in which at least one of the memory areas is in the form ofRAM.
 20. The device as claimed in one of claim 17 or 18, in which thepath traceback unit has the following components: a control unit; amultiplexer which is coupled via a control input to the control unit, inwhich case it is possible to use the control unit to select whetherinformation about the maximum likelihood path or about the respectivefurther concurrent path is selected by the first multiplexer, in whichcase the respective start state for the path traceback method within thefurther concurrent path can be supplied to a first input of the firstmultiplexer, in which case information as to whether a transition bit isintended to be inverted for the traceback of the further path can besupplied as a second input of the first multiplexer, in which case therespective time to which the start state relates can be supplied at athird input of the first multiplexer, in which case the respective startstate of the maximum likelihood path can be supplied at a fourth inputof the first multiplexer, and in which case the respective time to whichthe start state of the maximum likelihood path relates can be suppliedas a fifth input of the first multiplexer.
 21. The device as claimed inclaim 16 or 17, further comprising a memory with a memory area forstoring path traceback information; or having a second memory area forstoring soft input information for the decoding unit; or with a thirdmemory area for storing determined state metrics and state transitionmetrics;or with a fourth memory area for storing signal values which arcintended to be output, and reliability values associated with the signalvalues.